International Journal of Innovative Research in                 Electrical, Electronics, Instrumentation and Control Engineering

A monthly peer-reviewed online and print journal

ISSN Online 2321-2004
ISSN Print 2321-5526

Since  2013

Abstract: The integration level in today’s word is continuously increasing in VLSI chips. So that complexity of testing is a major challenge. That is because the internal chip modules have become increasingly midcult to access. There is a significant amount of the testing cost as compared to the total manufacturing cost. Hence there is a necessity to reduce the testing cost. The main factor is the time required to test the circuitry that has the biggest impact on testing cost of a chip. This time can be decreased by reducing the number of tests required to test the chip. So, we simply need to devise a test set that should be small in size. There is one way to generate a small test set is to compact a large test set parameters. The main drawback of the compaction results on the quality of the original test set. This aspect of compaction has motivated the work presented here with some methods of fault detection and avoidance techniques to test the circuit for a fault-free environment.

Keywords: Test circuits, Physical redundancy, Time redundancy, Monotonic logic, Self-checking circuits

PDF | DOI: 10.17148/IJIREEICE.2018.6115