Abstract: To speed up SoC integration and promote IP reusability, many bus-based communication architecture standards have emerged over the past several years. Verification of complex System-on-Chip (SoC) designs demands the need for a highly reusable testbench. The existing methodologies are Open Verification Methodology (OVM), Verification Methodology Manual (VMM) and many other which are tool dependent and not have greater flexibility for development of testbench. Universal Verification Methodology (UVM), the proposed one provides a class library for building advanced reusable verification environment. Advanced Extensible Interface (AXI) which is the most commonly used bus protocol is verified using UVM methodology. This paper also presents the different verification strategies such as Assertion based, Coverage driven, Random functional, Static functional, Dynamic functional and Equivalence Verification Simulation is performed using Questsim tool.

Keywords: SoC, UVM, AXI

| DOI: 10.17148/IJIREEICE.2021.9709