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International Journal of Innovative Research in
Electrical, Electronics, Instrumentation and Control Engineering

A monthly Peer-reviewed & Refereed journal

ISSN Online 2321-2004
ISSN Print 2321-5526

Since 2013

Performance Analysis of Fully-Depleted Silicon-On-Insulator (SOI) G4-FET and Gate-All-Around (GAA) MOSFETs

Md. Rakibul Alam, Md. Rais Uddin Mollah, Md. Ferdous Khan

Abstract: The performance of fully-depleted Silicon-On-Insulator (SOI) Four Gate Transistor (G4-FET) and Gate-All-Around (GAA) MOSFETs are investigated. Threshold voltage, Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), maximum drain current are calculated and compared.

Keywords: Silicon-on-Insulator (SOI), Four Gate Transistor (G4-FET), Gate-All-Around (GAA), Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL)


Downloads: PDF | DOI: 10.17148/IJIREEICE.2019.7301

Cite This:

[1] Md. Rakibul Alam, Md. Rais Uddin Mollah, Md. Ferdous Khan, "Performance Analysis of Fully-Depleted Silicon-On-Insulator (SOI) G4-FET and Gate-All-Around (GAA) MOSFETs," International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI 10.17148/IJIREEICE.2019.7301

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