Abstract: This paper provides an Optimized Arithmetic Logical Unit (ALU) with BIST capability, ALU comprising of different arithmetic operations and logical operations is implemented. ALU is used in many processing and computing devices, due to rapid development of technology not only the faster arithmetic unit is required but also less area and low power arithmetic units are needed and due to the increasing integration complexities of IC‘s the Optimized ALU implemented sometimes may malfunction, so testing capability must be provided and this is accomplished by Built In Self-Test (BIST) for Optimized ALU. In this project the implementation will be done in Encounter platform.

Keywords: ALU, BIST, Vedic Algorithm, Cadence Encounter, Xilinx.

| DOI: 10.17148/IJIREEICE.2020.8707