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Novel Technique on Channel Security using UART
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Abstract: This paper proposes a technique for implementing a UART (Universal Asynchronous receiver transmitter) with a new architecture such that the whole core can be modified for our desired specifications and can be integrated in a bigger design, wherever UART is necessary. This paper is implementing the design through Verilog HDL using Xilinx 14.2 design suite and it is tested on Spartan-6 FPGA after interfacing the circuit under test using PC with the help of RS-232 cable. The simulation results and the test results are supporting our proposal.
Keywords: UART, Verilog, FPGA, VLSI.
Keywords: UART, Verilog, FPGA, VLSI.
How to Cite:
[1] G Venkata Pavan Rama Sai Bharadwaj, A Vinay Krishna, M Siva Sai Krishna, Talari Akhil, โNovel Technique on Channel Security using UART,โ International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI: 10.17148/IJIREEICE.2016.4571
This work is licensed under a Creative Commons Attribution 4.0 International License.