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International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering
International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering A monthly Peer-reviewed & Refereed journal
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← Back to VOLUME 4, ISSUE 5, MAY 2016

LPVLSI Design – A Leakage Reduction Method for Portable Devices Applications: A Review

Sushma K H, Praveen J, Raghavendra Rao A

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Abstract: In our daily life, miniaturised and compact electronic devices are integral components. All devices need charging some amount of time. In discharging time, devices are in inactive state. Why electronic devices are become battery discharge ? Because of leakage current. Transistor size becomes smaller and smaller and also it becomes faster and faster because of high density and threshold voltage falls i.e.., leakage of current. As considered scaling of VLSI geometries, consumption of static power is more influencing than others. In the VLSI, demanding of scaling and static power. Designers using stacked sleep transistor without penalization in power setup, delay and performance in circuit.

Keywords: VLSI (very large scale integration), CMOS (complementary metal oxide semiconductor),sleep transistor, cadence virtuoso.

How to Cite:

[1] Sushma K H, Praveen J, Raghavendra Rao A, “LPVLSI Design – A Leakage Reduction Method for Portable Devices Applications: A Review,” International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI: 10.17148/IJIREEICE.2016.4504

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