LITERATURE REVIEW A Sustainable Approach to Low-Power Real-Time PLL Design Using Current-Starved VCO in 45-nm CMOS Technology

Abstract: Phase-Locked Loops (PLLs) are essential mixed-signal circuits for clock generation, frequency synthesis, synchronization, timing recovery, wireless communication, and energy-constrained embedded systems. As semiconductor technology scales, PLL designers must simultaneously address power consumption, phase noise, jitter, lock time, tuning range, supply sensitivity, process-voltage-temperature (PVT) variations, and implementation area. The voltage-controlled oscillator (VCO) is particularly important because its delay, current, gain, and noise directly influence the closed-loop behavior of the PLL. Current-starved voltage-controlled oscillators (CSVCOs) are attractive for low- power operation because the bias current of the delay stages can be controlled through the tuning voltage. This literature review examines 15 representative publications covering low-power PLLs, current-starved VCOs, 45-nm CMOS implementations, PVT-tolerant oscillator techniques, charge-pump design, ring-VCO PLLs, and recent supply-noise- insensitive PLL research. Particular attention is given to IEEE publications and recent work from 2024–2025. The review identifies a gap in the joint optimization of a complete 45-nm CSVCO-based PLL for low power, real-time locking, wide tuning, low phase noise, and robustness. The findings provide the technical basis for the proposed sustainable PLL design using Cadence Virtuoso.

Keywords: Phase-Locked Loop (PLL), Current-Starved VCO (CSVCO), ring oscillator, 45-nm CMOS, low power, real-time locking, phase noise, jitter, charge pump, PVT variation, supply-noise immunity.