Highly Efficient Hybrid Model Carry Select Adder with Power-Area-Delay Trade

Abstract: In this study, we offer a high speed design, a design with the smallest size compared to prior CSLAs, and two hybrid designs for Square root (SQRT) Carry Select Adder (CSLA). The first proposed architecture uses a new fast and merged add-one and multiplexing circuit to optimise the Binary to Excess-1 Converter (BEC)-based CSLA. This architecture, in addition to having a significantly lower area, delay, and energy consumption than the BEC CSLA, takes up about the same space as the best extant CSLA, the IR redundant Carry Generation and Selection scheme (IRCGS CSLA), while delivering a greater speed. The area-optimized architecture of IRCGS CSLA, which uses a new logic optimization while preserving speed, is the second suggested CSLA as the lowest-area design. To reduce the number of gates and produce a more compact architecture, this system employs multiplexer-based logic. Furthermore, experimental results reveal that Hybrid CSLAs are more favourable since they combine the advantages of both architectures. It can be coupled with a variety of parallel prefix adders to increase performance even further. Furthermore, the hybrid CSLAs surpass the best current design in all three area, delay, and energy metrics.

Keywords: Carry select adder, Parallel prefix adder, Ripple carry adder, Hybrid CSLA