High Speed and Energy Saving Carry Skip Adder

Abstract: VLSI technology is to optimize any type of digital architecture because this optimization is mainly used to enhance the various applications. A high speed and low energy carry skip adder (CSKA) structure has been proposed here. The speed enhancement is realized by applying concatenation and incrementation schemes to increase the efficiency of the conventional CSKA structure. Rather than utilizing the multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure increases the speed and energy factors of the adder. A hybrid variable structure reduces the power consumption without influencing the speed, is done. The proposed structures are estimated by comparing their speed, power, and area parameters with those of other adders in Xilinx ISE using VHDL. Keywords: Carry skip adder (CSKA), high performance, energy efficient, AOI/OAI, hybrid variable latency adder.