Hardware Implementation of Retinal Image Processing Algorithm on FPGA

Abstract: A methodology for implementing real-time DSP applications on a field programmable gate arrays (FPGA) using Xilinx System Generator (XSG) is presented. This paper outlines efficient hardware architecture for detection of exudates in retinal images. The proposed design comprises architecture for Sobel edge detection and segmentation method. The egde map image obtained is enhanced for its perception using contrast stretching. Further the image is segmented to detect the exudates. This design has been implemented on Virtex-II Pro (xc2vp30-7ff896 platform). The code is synthesized within ISE 9.2 development suite. The results obtained via hardware software co-simulation use limited FPGA resources at higher maximum frequency. Keywords: XSG, FPGA, Edge detection, Segmentation, Exudates.