Hardware efficient watermarking technique for finite state sequential circuit using STG

Abstract: Intellectual Property Protection (IPP) is very important for a design created by IP owner. For this, IP owner embeds watermark in its design. One such type of technique is suggested by Oliviera, in which modification of State Transition Graph (STG) of a digital circuit takes place in such a way that it is not possible for the intruder to find that there is a watermark embedded in the circuit. It is also possible to prove the piracy of the design in court-of-law. A method for state reduction in the watermarked circuit has been proposed in this paper. The comparison of simulation of non-watermarked, watermarked circuit with existing technique and the modified reduced state watermarked circuit is done using ModelSim Simulator. The Detection of Piracy can be done by using a counter circuit.

Keywords: Intellectual Property Protection, State Transition Graph, Watermark, Finite state machine, Signature sequence