Fractional N-Phase Locked Loop using VLSI Technology

Abstract: Literature survey of Phase Locked Loop reflects that many researchers have applied different techniques like digital and analog simulation by applying mathematical/logical relations to design the Phase Locked Loop (PLL) . Researchers have undertaken different systems, processes or phenomena with regard to design and attempted to find the unknown parameters and analyzed PLL. Since in the real world today VLSI/CMOS is in very much in demand, it is observed that very few researchers have undertaken the work for designing PLL using CMOS/VLSI technology, ,after the careful study of reported work. In the proposed work, low power PLL with multiple outputs is designed with stability of system and there are no fractional spurs in the output spectrum of the fractional-N phase locked loop.

Keywords: Phase Locked Loop; Sigma-Delta modulation; Frequency Synthesizer; Fractional-N; Phase Noise