Design of Testable Reversible ALU using QCA Multiplexers

Abstract: International Technology Roadmap for Semiconductors (ITRS) has indicated several new technologies alternative for CMOS nanotechnology, some of these include Resonant Tunneling Diodes (RTDs), Single Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL). Among these, QCA seems to be the most promising emerging technology, as a viable alternative to CMOS. ALU is a fundamental building block of a central processing unit (CPU) in any computing system. Using reversible logic gates instead of traditional logic AND/OR gates, a reversible ALU whose function is the same as traditional ALU is constructed. Programmable reversible logic gates are realized in Verilog HDL, the simulation results have been verified using the QCADesigner. Reversible logic has ability to reduce the power dissipation which is the main requirement in low power digital design. By using the inverse property of reversible logic, all the inputs can be regenerated at the outputs. Thus, by comparing the original inputs with the regenerated inputs, the faults in reversible circuits can be detected. Minimization of the garbage outputs is one of the main goals in reversible logic design and synthesis. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers. The reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible- ALU‘s programmability/testability.

Keywords: RTD, SET, TPL, QCA, Verilog HDL, reversible multiplexer (RM), reversible ALU.