Abstract: The stability and power consumption of SRAM cell are the important factors in current technologies due to variability and voltage scaling. It has become a part of system-on-chip in modern VLSI designs. The existing SRAM cell designs are power hungry and have low performance for fast computing applications. In the proposed work a low power 8T SRAM cell is designed based on power gating mechanism. The Conventional 6T SRAM cell is very much prone to noise during read operation. To overcome the read SNM problem in 6T SRAM cell, configurations of 8T SRAM cells is proposed. 8T SRAM design also improves the cell stability but suffer from bitline leakage noise. Power gated VDD design technique have been employed to reduce the power consumed by the SRAM cell. The proposed design is compared with the conventional 6T SRAM cell. The results show that the gated based 8T SRAM cell is the best performer in terms of power consumption and power delay product. The power gated 8T SRAM cell consumes less power than the conventional 6T SRAM cell and also has a better power-delay-product.
Keywords: SRAM, Power Gating, PDP, SoC
| DOI: 10.17148/IJIREEICE.2019.7414