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Design of low power pipelined ADC
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Abstract: A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.
Keywords: Comparator, Op-amp, SUB-ADC, MDAC, SNDR, ENOB
Keywords: Comparator, Op-amp, SUB-ADC, MDAC, SNDR, ENOB
How to Cite:
[1] AMIT MAHESHWARI, GAURAV GUPTA, βDesign of low power pipelined ADC,β International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI: 10.17148/IJIREEICE.2014.21219
This work is licensed under a Creative Commons Attribution 4.0 International License.