Design of Efficient adder Circuits in Sub Threshold Region

Abstract: Sub threshold (leakage or cut-off) currents are a necessary in traditional VLSI design methodologies. Ultra- low power applications such as micro-sensor networks, pacemakers, and many portable devices require extreme energy constraints for longer battery life. Increasing the battery life can provide a competitive advantage in the marketplace. Traditionally, reducing the power supply voltage is regarded as the most effective means of reducing power consumption. Therefore, digital circuits operating in the sub threshold region offer a promising solution for emerging portable applications that require tremendously low energy consumption. The proposed work is to compare the performance of various CMOS circuits such as inverter, Half adder, Full adder between conventional conduction and sub threshold conduction in terms of power and delay. As a result the circuits under sub threshold conduction is efficient than conventional because power of sub threshold circuit is less than conventional circuit. The circuits are design using tanner tool.

Keywords: Sub threshold conduction, combinational circuits, low power.