Design of area efficient chip layout of fractional N-phase locked loop using VLSI technology. A review

Abstract: In communication system power is one of the most important parameter. Power is the amount to function or generating out energy. This means that it is a way of measuring how fast a function can be carried out. So power has become one of the most important parameter in various communication systems such as optical data links, wireless products, microprocessor. This topic presents the design of an area efficient chip layout of fractional-N phase locked loop for Bluetooth application using VLSI technology. Phase locked loop is a control system that generates an output signal whose phase is realated to the phase of an input signal. This phase locked loop is designed using VLSI technology, which offers high speed performance at low power. Loop filter and Sigma-Delta modulator are the most important factors in improving the performance of fractional-N phase locked loop. The digital Sigma- Delta modulator provides a useful noise shaping for the phase noise introduced by the fractional division operation, while the loop filter bandwidth limits the speed of switching time between the synthesized frequencies.

Keywords: Phase locked loop, sigma delta modulator, Divide by N- counter Voltage controlled oscillator.