Abstract: In the previous full adder circuits, it is occupying more area and power consumption. In this project the adder circuit is designed by using the minimum number of gates and error tolerant adders to reduce the power consumption and to use the area efficiently. The two versions of 16-bit ETA’s were used. Such as Low power and area efficient Error Tolerant Adder (LETA) and Improved Low power and area efficient Error Tolerant Adder (ILETA). It uses the Most Significant Bit (MSB) to access the data. In our proposed system we have used the Digital Image Processing (DIP), and this have used in imaging processing and image blending algorithm is implemented and it is simulated by using XILINX with the mentioned advantages. In these proposed ETA’s, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using a proposed IFAs and existing modified full Adder (MFA), respectively. The proposed and existing Error Tolerant Adders (ETA) are implemented using asynthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology and Verilog hardware description language (HDL). A new performance metric namely power and error product (PEP) is suggest in order to evaluate the approximate adders in terms of error and power metrics. It is found that the proposed ILETA achieves a low PEP of 1.05×10 2 compared with other ETA’s.

| DOI: 10.17148/IJIREEICE.2023.11310