International Journal of Innovative Research in                 Electrical, Electronics, Instrumentation and Control Engineering

A monthly peer-reviewed online and print journal

ISSN Online 2321-2004
ISSN Print 2321-5526

Since  2013

Abstract: This paper describes the design of a dual and quad core pipelined Reduced Instruction Set Computer (RISC) processor using Verilog HDL and its implementation in vertex 6 FPGA. Dual and quad core processor consumes less power with high efficiency. The processor has instruction and data memory spaces are both physically and logically separate called Harvard memory architecture. Single core have 5 bit opcode, 23 set of instructions and it is designed by using the pipelining which increase speed of processor. The processor design is done by using RISC architecture which involves Registers (General purpose), Arithmetic and Logical Unit (ALU), Memory (Data and program) with pipeline techniques. Load and Store instructions used to access memory. The comparison of dual and quad core RISC architecture in terms of structure and power consumption is explained in paper with design summary.

Keywords:  RISC characteristics, Pipelining, Memory, Load and Store, dual core processor, quad core processor


PDF | DOI: 10.17148/IJIREEICE.2018.6114