International Journal of Innovative Research in                 Electrical, Electronics, Instrumentation and Control Engineering

A monthly Peer-reviewed / Refereed journal

ISSN Online 2321-2004
ISSN Print 2321-5526

Since  2013

Abstract: In today’s world demand of low power devices is increasing and the reason behind this is scaling of CMOS technology. Due to the scaling, size of the chip decreases and number of transistor in system on chip (SOC) increases and this phenomenon also apply on memories that are used in SOC. Memories are the power hungry devices in any digital system but today no digital system can be completed without memories. However, the transistor miniaturization also introduces many new challenges in very large-scale integrated (VLSI) circuit design. So in future the need of low power memories is increasing and to design low power memories leakage power is attentive parameter to design low power devices because it plays a major role in increasing the total power consumption of the devices.
In this project, Dual Sleep technique is used recently it is very famous in academia and industry. It is a power reducing technique that helps in reducing leakage power in the SRAM by turning of the inactive circuit domains. Designing and calculation of parameters of simple SRAM, Memristor based SRAM and Dual Sleep based Memristor SRAM has been done with CMOS Design tool and that will do at 45 nm technology.

keywords: Low power, Speed, SRAM, Non Volitle Memory, CMOS, Memristor, MTCMOS, Dual Sleep.

PDF | DOI: 10.17148/IJIREEICE.2022.10230

Open chat