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International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering
International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering A monthly Peer-reviewed & Refereed journal
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← Back to VOLUME 4, ISSUE 7, JULY 2016

BIST for Memory with Address and Syndrome Compression

Ajinkya R. Kapse, Poorvi K. Joshi

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Abstract: Because of fixed number of pins, buit-in self-test (BIST) for embedded RAMs ordinarily sends out the diagnostic information serially, which increases the total diagnostic time. The proposed BIST decrease the diagnostic time by lessening number of bits required for sending out defective address and fault syndrome. The fault address bits are diminished by sending out differential address and fault syndrome is compressed utilizing march element based (MEB) compression. Simulation results demonstrate that the compression ratio is around 43.01% for a 4KΓ—16-bit memory.

Keywords: Random Access Memories; built-in self-test; diagnosis; compression

How to Cite:

[1] Ajinkya R. Kapse, Poorvi K. Joshi, β€œBIST for Memory with Address and Syndrome Compression,” International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI: 10.17148/IJIREEICE.2016.4741

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