An efficient low power L2 cache architecture using pre-computation logic

Abstract: Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficient microprocessor, it is important to optimize cache energy consumption. High-performance microprocessors employ cache write-through policy for performance improvement and at the same time achieving good tolerance to soft errors in on-chip caches. Write-through policy also consumes large power due to the increased access to caches in different level during write operation. In this paper, we propose an efficient low power cache design referred to as way-tagged cache using Pre-Computation Logic. The cache architecture is designed using a Pre-Computational technique in place of the comparators. This helps to achieve low power consumption than existing technique.

Keywords: Cache, low power, Pre-computation logic, way-tagged cache, write-through policy.