Abstract: An Hybrid technique to the circuit implementation of 9-bit analog-to-digital (ADC) converter is proposed, This method demonstrates a simple technique to increase speed of successive approximation ADC’s that require as few as 4 comparisons for 9 bit conversion. This technique doubles the conversion speed of conventional successive approximation technique. The approach divides input range into 32-quantization cells, separated by 31 boundary points. A 5-bit binary code 00000 to 11111 is assigned to each cell. A normal successive approximation converter requires 9 comparisons for 9-bit quantization, while proposed technique reduces number of comparison requirements to 4 comparisons. An experimental prototype of 9-bit ADC using proposed technique was implemented using µp 8085. Use of Microprocessor has greatly reduced the hardware requirement and cost. This technique is best suitable when high speed combined with high resolution is required. The ADC Results of 10-bit prototype is presented. The results show that the ADC exhibits a maximum DNL of 0.47LSB and a maximum INL of 0.5LSB.
Keyword: Analog to digital converter, digital to analog converter, flash ADC, Microprocessor, Successive approximation.
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