Abstract: High resolution analog to digital converters have been based on self–calibrated successive approximation technique. But successive approximation technique ADCs are unsuitable for high speed conversions. Flash converters are popular for high speed applications up to 8-bit resolutions, conversion resolution higher than 8- bits, flash architecture require large number of comparators, hence this architecture is not suitable for high resolution ADCs. In this case, however, this paper demonstrates that, effective combination of successive approximation and parallel quantization techniques have to be used for optimizing the number of comparator requirements while maintaining conversion speed. Such optimization is achieved through a systematic design process. A simple Analog-to-Digital conversion technique, which provides superior conversion speed to that of successive approximation converter, is presented. In this approach, the increased conversion speed is achieved by effective combination of parallel quantization and successive approximation techniques. An 12-bit flash quantizer uses 212-1 comparators, where as proposed architecture uses only 256 comparators. A successive approximation converter requires 12 comparisons for 12-bit quantization, while proposed technique converts an analog signal into 12-bit equivalent digital code in 12 comparisons. The technique uses less number of comparators while maintaining the speed. Therefore this architecture is best suitable when high speed combined with high resolution is required. Result of 12-bit prototype is presented.
Keyword: Analog to digital converter, digital to analog converter, flash ADC, Microprocessor, Successive approximation.