Abstract: To achieve a very fast digital devices with reduced power usage is an important for the VLSI circuit designers and manufacturers. For the most part of the digital circuit design carried out using the multiplier, where it is used more power consuming component in the electronic circuit design. The multiplication operation has been carried out by the process of shift and add method. Due to the improvement among various adders, which the way for the increase in execution rate of the multipliers. Parallel multiplication algorithms are used in the combinational circuits. And don’t contain feedback structures. The circuit is developed by VHDL and functions were validated based on the simulations obtained utilizing Xilinx. In this project, the enhancement in WTM using the KSA and the Modified Approximate Full Adder concepts is done.

| DOI: 10.17148/IJIREEICE.2023.11303