Verification & Design Techniques Used in a Graduate Level VHDL Course

Abstract: The use of the VHSIC Hardware Description Language (VHDL) has become very important to the simulation and implementation of digital systems in both industry and educational settings. Al-though VHDL is a powerful language with many capabilities, it has downfalls when considering the difficulty in learning the language as well as its limited capabilities for transitioning a design from initial concept to design entry and verification stages. This paper discusses techniques used to teach the VHDL design methodology to graduate students, as well as methods used to go through a complete design cycle from initial concept to final implementation. VHDL design techniques were developed using various projects and homework assignments, and different approaches to implementing the same function allowed direct comparisons of the speed and size of the designs. Different processes for taking a design from ini-tial concept through chip implementation were discussed, and one example of the process is discussed here. This paper describes the implementation of full adder using VHDL technology which meets less complexity requirement ,it also shows how efficiently digital system ie Full Adder is implemented upto layout level results shows technological map RTL view ,chip floor plan ,chip layout ,output waveforms showing voltage Vs time relations and verification of truth table .

Keywords: VHDL, RTL view, HDL