Abstract: Static Random Access Memory is a volatile type of memory used for enhancing the data rate of operations in devices for outer space applications. The semiconductor devices might be damaged or would experience a malfunction resulting in software errors due to avionics and radiation conditions. The ionising particles in space may lead to the state of change in the memory cell and distract the multiple bit operations in the written mode. This phenomenon is known as a single event upset (SEU). Scientific Advancements in various technologies and architecture design of SRAM are being introduced. Consequently, SEU type of errors could not be prevented but could be minimized to a significant extent. Here a 14 T based 3 terminal and 4 terminal CMOS SRAM cell is designed and is compared with a 15T 3 terminal and 4 terminal SRAM cell. Circuits are implemented using Tanner 16.5 version. Using MATLAB, performance metrics like SNM, read delay and write delay are observed. The proposed 15T SRAM cell improves the performance in terms of deviation in HSNM by 79%, 2% from 13T and proposed 14T SRAM cells during the rise in temperature. The CMOS SRAM cell is designed to minimize leakage by reducing the operating voltage. The proposed cells are also implemented using FinFET, CNTFET, and GNRFET technologies in the development stage. In the proposed 15T SRAM cell, power is reduced by 12.8%, and the delay factor reduced by 13.2% compared to 13T SRAM cell.
Keywords: SRAM, RHBD, HSNM, SEU, FINFET, CNTFET, GNRFET.
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