Systolic All One Polynomial Multiplier for Reed-Solomon Encoder

Abstract: Irreducible polynomial algorithm for modular multiplication with a large modulus has been widely used for error control coding in secured data communication. This paper presents an area-time efficient bit-parallel systolic multiplication architecture over GF (2m) based on irreducible all-one polynomial. This circuit is constructed by identical cells, each of which consists of one two-input AND gate, one two-input XOR gate and Bit shift cell. The proposed architecture is well suited to VLSI systems due to their regular interconnection pattern and modular structure.

Keywords: Irreducible Polynomial, systolic array, finite field, All-One Polynomial(AOP)