Simulation of a Cascaded Multilevel Inverter Topology with Reduced Number of Switches

Abstract: This paper proposes a topology of a cascaded multilevel inverter that utilizes less number of switches than the conventional topology. Therefore with reduced number of switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). As the numbers of switches are reduced, both conduction and switching losses will be decreased and electromagnetic interference is reduced, which leads to increase the efficiency of converter. The proposed inverter focus extends to produces number of voltage levels in the same number of the voltage source and reduced number of switches compared to the conventional inverters. Thus the inverter will be simulated with the implementation of appropriate pulse width modulation (PWM) techniques strategy to generate firing pulses and ensure the desired operation of the power modules techniques and its effect on the harmonic spectrum will be analyzed. The system will be modeled with the help of MATLAB/SIMULINK

Keywords: Cascaded multilevel inverter, Matrix topology, PWM Strategy.