Phase Locked Loop using VLSI Technology For Wireless Communication

Abstract: Literature survey of Phase Locked Loop reflects that many researchers have applied different techniques like digital and analog simulation by applying mathematical/logical relations to design the Phase Locked Loop (PLL). Researchers have undertaken different systems, processes or phenomena with regard to design and attempted to find the unknown parameters and analysed PLL. Since in the real world today VLSI/CMOS is in very much in demand, it is observed that very few researchers have undertaken the work for designing PLL using CMOS/VLSI technology. The PLL is designed using 45 nm CMOS/VLSI technology in microwind 3.1. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm.

Keywords: Phase locked loop (PLL), voltage-controlled oscillator (VCO), 45nm technology, VLSI technology, low power