Memory Debug Using Bist

Abstract: Built –in self test (BIST) are best tested in Embedded Memories such as RAMs and ROMs. The use of BIST is for manufacturing or production testing with additional features for diagnostics and debug [1].This paper present a study on memory debug methodology using BIST in system-on-chip (SOC) product development and yield ramp-up and describes diagnosis techniques during rapid development of semiconductor memories for catching the design and manufacturing failures and improving over all yield and quality[2]. It also covers MARCH based memory diagnosis algorithm which locate fault cells also identified their types, using the proposed algorithm stuck-at-faults, state coupling faults, transition faults can be distinguished. With all of these, defect diagnosis and Field application (FA) engineer can be performed automatically using the fault patterns, reducing the time in yield improvement [3]. The main purpose of this algorithm is accelerating fault diagnosis for semiconductor memories. Design is described using verilog HDL simulation is carried out using Modelsim simulator synthesis is done using Xilinx ISE Implementation is done on Spartan 3e FPGA .

Keywords: Memory debug algorithm , March 17n algorithm , BIST