Low Transition Test Pattern Generation for Path Delay and Stuck-at-Faults

Abstract: A low transition test pattern generation for path delay and stuck-at-faults is proposed. Main challenges in generating compressed tests are reduced test data volume along with low transition pattern sequence. The proposed work uses BS-LFSR (Bit Swapping-Linear Feedback Shift Register) for generating test pattern. The basic approach that the paper uses modifies initially random seeds for the BS-LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in the proposed method also selects detectable path delay and stuck-at faults to address the presence of undetectable path delay and stuck-at faults in the set of target faults. The Bit-Swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 Multiplexer and used to generate test patterns which reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. Further, undetectable fault are covered using observation point insertion for improving the fault coverage. Experimental results for fault coverage are analyzed for path delay and stuck-at faults in benchmark circuits.

Keywords: BS-LFSR, Test Data Compression, Test Generation, Low-Power Test, Test Point Insertion