Abstract: To implement Approximate computing has emerged as a potential solution for the design of energy-efficient digital systems. Applications such as multimedia, recognition and data mining are inherently error-tolerant and do not require a perfect accuracy in computation. Multipliers are key arithmetic circuits in many of these applications including Digital Signal Processing (DSP). Here a novel approximate multiplier design with low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed Spurious-Power Suppression Technique (SPST) approximate adder that limits its carry propagation and dramatically reduces the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the Most Significant Part and Least Significant Part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.

Keywords: Approximate Multiplier, SPST adder and error recovery.

| DOI: 10.17148/IJIREEICE.2020.8811