Abstract: D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible, utilized in advanced coordinated circuits. As a constant research center, various types of zero flip-flops have been explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can come down to low power-defer item.To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream.This project includes to design and development of a Low Power Dynamic Power Based True Single Phase D Flip Flop [TSPC] for High Performance Application using Cadence Tool. The design has been tested and verified using Cadence Virtuoso. The developed TSPC D Flip Flop model can be used in the design of sequential circuits with enhanced performance.

Keywords: TSPC D Flip-Flop, Low Power VLSI, Design, High-Speed Sequential, Circuits, Cadence Virtuoso Simulation

Downloads: | DOI: 10.17148/IJIREEICE.2025.13906