High Speed and Low Area FIR Filter Implementation Based on Dadda Multiplier Design

Abstract: Today every circuit has to face the power consumption issue for both portable devices aiming at large battery life and high-end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that during logic synthesis power tracks well with area. This means that a larger design will generally consume more power. The multiplier is an important kernel of digital signal processors. Because of the circuit complexity, the power consumption and area are the two important design considerations of the multiplier. In this paper a High Speed & low area architecture for the Dadda Multiplier is proposed. For getting the High Speed & lower area architecture, the modifications made to the conventional architecture consist of the reduction in switching activities of the major blocks of the multiplier, which includes the reduction in switching activity of the adder and counter. This architecture is used in FIR Filter Design. The simulation result for 8 bit multipliers & four tap Filters shows that the proposed low Area & Delay architecture lowers the total Area & Delay when compared to the Booth Multiplier and Dadda Multiplier architecture based Filter.

Keywords: Finite Impulse Response (FIR), Dadda Multiplier, Booth Multiplier.