Hardware Accelerators for FFT Optimization: A Review of Genetic Algorithm-Based Approaches

Abstract: Fast Fourier Transform (FFT) algorithms are fundamental in a wide range of digital signal processing applications, including audio analysis, image processing, and telecommunications. However, optimizing FFT implementations for speed, efficiency, and hardware utilization remains a complex task due to the numerous tunable architectural parameters such as radix type, stage configuration, word length, and pipeline depth. This paper presents the design and implementation of a hardware accelerator optimized through a Genetic Algorithm (GA), which intelligently explores the design space to identify parameter sets that yield optimal performance. The GA operates by encoding FFT configuration parameters into chromosomes and evolving them based on a fitness function that considers throughput, latency, power efficiency, and resource usage. A hardware model of the FFT accelerator is developed and evaluated through simulations to measure performance improvements against traditional fixed-parameter designs. Results demonstrate that GA-optimized FFT configurations lead to notable gains in processing speed and computational efficiency, validating the effectiveness of evolutionary algorithms in hardware design optimization. This work showcases the synergy between artificial intelligence and hardware engineering for advanced digital signal processing systems.

Keywords: Genetic Algorithm (GA), Hardware Acceleration, Fast Fourier Transform (FFT), Parameter Optimization, Digital Signal Processing (DSP), High-Level Synthesis, Hardware Design Automation, Signal Processing Architecture