GUI Based Complex Test Pattern Generation for High Speed Fault Diagnosis in Memory Chips

Abstract: The memory blocks testing is a separate testing procedure followed in VLSI testing. The memory blocks testing involve writing a specific bit sequences in the memory locations and reading them again. This type of test is called March test.
A particular March test consists of a sequence of writes followed by reads with increasing or decreasing address. For

example the March C- test has the following test pattern.
There are several test circuits available for testing the memory chips. However no test setup is developed so far for testing the memory blocks inside the FPGA. The BRAM blocks of FPGA are designed to work at much higher frequency than the FPGA core logic. Hence testing the BRAMs at higher speed is essential. The conventional memory test circuits cannot be used for this purpose. Hence the proposed work develops a memory testing tool based on March tests for FPGA based BRAM (block RAM testing).
The code modules for March test generator shall be developed in VHDL and shall be synthesized for Xilinx Spartan 3 Family device. A PC based GUI t.ool shall send command to FPGA using serial port for selecting the type of test. The FPGA core gets the command through UART and performs the appropriate and sends the test report back to PC. Generally, in the studies of microelectronics engineer the approach of IC testing remains very theoretical. Only few concrete practices are commonly done and generally laboratory experiences are limited to the use of CAD tools. For this purpose, in our teaching department, we develop an experiment allowing a concrete learning of IC testing dedicated to the test of commercial memory chips. Through this environment, our students reached a better knowledge of the connection between the test sequences and the detected faults.