Flood Monitoring and Deduction from Satellite Images using Modified Deep Learning Techniques

Abstract: Shift register are commonly used in many applications, such as digital filters, communication receivers, and image processing ICs. The proposed work uses a decoder enabled pulsed latch to design a low-power and area-efficient shift register. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal.The area and power consumption are reduced by replacing flip- flops with pulsed latches. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 16-bit shift register using pulsed latches was synthesized using Xilinx FPGA. The proposed shift register saves area and power compared to the conventional shift register with flip-flops. A 256bit Bi-Directional shift register was fabricated using a 65nm CMOS Process. It reduces area by 22.3% power consumption by 11.2% compared to low power area andshift register.

Keywords: Area efficient, Bi-Directional Shift, Flip flop, Pulsed clock, Pulsed latch.