Abstract: The Intellectual Property (IP) blocks are designed by hundreds of IP vendors distributed across the world. Such IPs cannot be assumed trusted as Trojans can be maliciously inserted into them and could be used in military, financial and other critical applications. It is extremely difficult to detect Trojans in third-party IPs simply with conventional verification methods as well as methods developed for detecting Trojans in fabricated ICs. The transfer of provably trustworthy modules between hardware IP producers and consumers, and discuss what it might mean for a device to be considered “secure”. We outline a semantic model representing the constructs permissible in a Verilog Hardware Description Language (HDL) and show how this model can be used to reason about the trustworthiness of circuits represented at the Register-Transfer Level (RTL). Identifying Suspicious Signals (SS) with formal verification, coverage analysis and Structural tests is area of focus.

Keywords: HDL, RTL, IP, Trojans, secure, formal verification, coverage analysis, Structural tests.

| DOI: 10.17148/IJIREEICE.2018.694