Abstract:  Linear-Feedback Register (LFSR) based counters are found to be suited for many applications which uses large arrays of counters and may also improve the performance compared with the traditional binary based counters. In order to decode the count order into binary, improved logic is needed which makes system-on-chip designs to be unfeasible. This paper presents a counter design supported by multiple LFSR stages that has the benefits of a single-stage LFSR but the essential decoding logic scales logarithmically with the number of stages as against exponentially with the number of bits with other methods. A four-stage four-bit LFSR based counter was designed and proof of concept was fabricated in 90nm CMOS technology and was characterized during a time-to-digital converter application at 800 MHz.

 
Keywords: Binary counters, decoding logic, event counters, Linear-Feedback Register (LFSR), single-photon detection

 

| DOI: 10.17148/IJIREEICE.2019.8412