Design of High speed, Low Power Pipelined ADC

Abstract: An 8-bit pipelined analog-to digital converter (ADC) is designed in this paper. The pipelined architecture realizes the high-speed and high-resolution . To reduce some complexities of flash ADC pipeline ADC is used. The calibration schemes of pipelined ADC limit absolute and relative accuracy. Deviations in residue amplifier gain results due to low intrinsic gain of transistors, and mismatching between all the capacitors of capacitance 1pF result in both deviations in residue amplifier gain and DAC nonlinearity in a pipelined ADC.

Keywords: Comparator, Folded Opamp, SUB-ADC,MDAC, Digital Error Correction block(DEC), Time Alignment Block