Abstract:  In this paper, we have presented the design, synthesis and simulation of 32-bit single precision floating point and Galois Field Multiplier using Wave Pipelining. Wave pipelining is a circuit design technique which allows digital synchronous systems to be clocked at rates higher than conventional pipelining techniques. Floating point multiplier is based on IEEE 754 standard which consist of 1-sign bit, 8-exponent bits and 23-mantissa (significand) bits. IEEE 754 standard works for addition, subtraction, multiplication and division, we use multiplication based on this standard. Galois Field multipliers have been widely used in coding theory and cryptography. The Galois Field Theory (GFT) which is used to design this multiplier deals with binary numbers, has the properties of a mathematical “field,” and are finite in scope. Many Galois operations such as addition and multiplication are common and match those of regular math. These operations are particularly, handy for checking multiplication results. Finally, Synthesis and simulation of these multiplier designs has been done in Xilinx ISE 13.1 simulator and the coding of the design is done in VHDL language. The delay obtained is 19.418nsec and 4.071nsec for Floating point multiplier and galois field multiplier respectively.

Keywords: Floating Point, IEEE 754, Wave Pipelining, Galois Field Theory, VHDL.

| DOI: 10.17148/IJIREEICE.2018.6515