Design and Analysis of Data Path Elements using Low Power State Retention Technique

Abstract: Most of the portable systems, such as cellular communication devices, and laptop computers operate from a limited power supply. The extension of battery-based operation time is a significant design goal which can be made possible by controlling the leakage current flowing through the CMOS circuit. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when the devices are in idle state. In this work a new circuit technique called LPSR technique is proposed to reduce threshold leakage power as well as total power in CMOS circuits. This proposed technique reduces maximum amount of leakage power during deep sleep mode, maximum power during dynamic mode and a provision of preserving state in low power sleep mode. Finally earlier well known techniques for leakage reduction and state retention are compared with this technique. Circuit designing, simulation and low power performance evaluation is done using CMOS technology files in Tanner EDA tool.

Keywords: Dynamic Power, Leakage Current, Low Power State Retention (LPSR), Power Dissipation, State Retention, Static Power.