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Arithmetic Coder Architecture used in SPIHT image compression
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Abstract: A Memory-efficient high throughput architecture of arithmetic coder for the set partitioning in hierarchical trees (SPIHT) image compression is proposed in this paper. In this architecture optimizations at different levels of arithmetic coding gives good image compression with high PSNR.
Keywords: Arithmetic coding, Peak Signal to Noise ratio (PSNR), Set Partitioning in Hierarchical Trees (SPIHT), VLSI Arithmetic coder architecture, Wavelet.
Keywords: Arithmetic coding, Peak Signal to Noise ratio (PSNR), Set Partitioning in Hierarchical Trees (SPIHT), VLSI Arithmetic coder architecture, Wavelet.
How to Cite:
[1] Rahila I. Mulla, Prof. Ms. R.R. Jagtap, βArithmetic Coder Architecture used in SPIHT image compression,β International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI: 10.17148/IJIREEICE.2017.51018
This work is licensed under a Creative Commons Attribution 4.0 International License.