Area-Delay Efficient Reconfigurable FIR Filter Architecture

Abstract: Transpose form finite impulse response (FIR) filter based on block formulation method can be used for reconfigurable applications. This reconfigurable FIR filter architecture realization is area, delay and power efficient. Transpose form finite impulse response filters are inherently pipelined and support multiple constant multiplication (MCM) technique that results in significant saving of computation. By block formulation method data samples in fixed size blocks are processed consecutively. General multiplier based architecture for transpose form configuration of filter, for which efficient multiplication can be performed by dadda multiplier in terms of area, delay and power. Reconfigurable FIR filter is implemented using VHDL language by Xilinx software. Keywords: Transpose form, Block formulation, Reconfigurable, Multiple Constant Multiplication, Dadda multiplier.