A Novel Six-Transistor SRAM Cell with Low Power Consumption

Abstract: In this paper, two static random access memory (SRAM) cells that reduce the static po wer dissipation due to gate and sub threshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lower the gate leakage current. It reduces the sub threshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the sub threshold leakage while maintaining performance. Analysis is done by comparing the power consumed by the different SRAM designs. The performance of the proposed designs can be analyzed with (1.25μm CMOS) T-spice tool. The results showed that PP-SRAM designs consumed less power compared to other designs.

Keywords: Dual threshold, gate leakage, low-power, static power, static random access memory (SRAM) cell, tunneling current.