Abstract— Semiconductor memories are considered one of the most important aspects of modern VLSI Systems. Memories are the most important universal components in System on chip today. Almost all SOC’s contain some type of embedded memories, such as ROM, RAM, DRAM and flash memory. Due to use of deep micron technology the cells are becoming more susceptible to manufacturing defects. Semiconductor memories will occupy the 90% of the total chip area by 2016. Testing the memory IP in SOC becomes more important because the memory density higher than the logic part, which means the chance to have a defect, is higher in memory. The quality of embedded memory dominates the overall quality and profitably of the whole chip. The BIST methodologies offer solutions for testability of embedded memories and minimize the embedded memory tester’s requirements and reduce memory test time.
A novel BIRA approach that focuses on a 100% repair rate and a minimal area overhead is proposed in this paper. In the modified method, depending on the error sensitivity and presetting a threshold, the rows with more errors are automatically replaced. After replacement any fault which is not recovered are replaced with column spare wires. Thus minimal time is only required. Our experimental results confirm that the modified approach exhibits outstanding performance for delay that have 100% repair rates are designed using the tool Xilinx14.2. Coding is done using VHDL and simulation is verified using Xilinx ISE Design Suite. The software used is XILINIX ISE simulator. Implemented using VHDL module.

Keywords: Built-in redundancy analysis (BIRA), area overhead, redundancy analysis (RA).

| DOI: 10.17148/IJIREEICE.2021.9723