Abstract: For data transmission, an ideal communication relies on Low Power Design. Systolic array multiplier with the reversible logic is widely known among those techniques for synchronizing signals in DSP processor applications. Low power circuit design yields many favorable conditions like increased performance, system capacity, minimized cost etc. Reversible logic is a phenomenal approach to reduce heat dissipation and information loss. Among basic arithmetic operations, Multiplication demands more processing time and seek complex hardware. As Conventional Systolic Array Multiplier is designed using irreversible logic gates, there is undesired power dissipation. So, to improvise this downside, this paper illuminates the design of low power Systolic Array Multiplier using reversible logic gates which performs data processing in Parallelism manner . Power, delay, garbage outputs and quantum cost is calculated mathematically in this paper. Finally, Cadence Virtuoso is used to obtain simulation results. 25mW is the power for the proposed design when the power of individual components is added theoretically. The overall power of the circuit is 14 ?W.
Keywords: Garbage Outputs (GO), Quantum Cost (QC), Multiplier cell(MC), Peres Full Adder (PFA), Peres gate (PG), Toffoli gate(TG).