Abstract: In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a Multiplier–Accumulator (MAC unit). Design of MAC unit consists of Multiplier unit, Adder and Accumulator. This Paper focuses on review of 64-bit MAC (Multiplier and Accumulator) unit based on Vedic Mathematics using VHDL. Proposed multiplier will be design by using technique of Vedic mathematics and the rule (sutra), Urdhva Tiryakbhyam will be used for enhancing the speed of multiplier. Pipeline is one way of improving the overall processing performance of a multiplier or any processor. Here, Pipeline design will be use to increase the speed of the MAC unit, also it can perform more than one operation in a single time. Design, synthesis and simulation of 64-bit MAC unit will be done using XILINX ISE 14.5. Coding of the proposed design will be done in VHDL (Very high Speed Integrated Circuit Hardware Description Language).

Keywords: MAC, Vedic Mathematics, XILINX ISE, VHDL.