Abstract: Orthogonal Latin Square (OLS) codes that provide low latency decoding and a modular construction. For some applications, like multimedia or signal processing, the effect of errors on the memory bits can be very different depending on their position on the word. Therefore, in these cases, it is more effective to provide different degrees of error correction for the different bits. This is done with Unequal Error Protection (UEP) codes. In this paper, UEP codes are derived from Double Error Correction (DEC) Orthogonal Latin Square (OLS) codes. The derived codes are implemented for an FPGA platform to evaluate the decoder complexity and latency. The OLSC Project has two major Process Encoder and Decoder. In the Decoder Part we modified the Syndrome Computation unit as well as we designed a Complete Setup of transmitter and Receiver via Encoder and Decoder. The results show that the new codes can be implemented with lower decoding delay than traditional SEC-DED codes and with a cost similar to that of both DEC OLS and SEC-DED codes. The Proposed encoder and decoder are done by Verilog HDL and Simulated by Modelsim 6.4 c and synthesized by Xilinx tool.
Keywords: DEP, UEP, OLS, Majority logic decoding.